System Verilog

On this page you will find a series of tutorials introducing SystemVerilog for FPGA design and verification. These tutorials take you through all the steps required to start using SystemVerilog and are aimed at total beginners.

If you haven’t already done so, it is recommended that you read the posts which introduce the FPGA development process first. These give an overview of all the stages required to design an FPGA. This information will give you some important basic background knowledge which will help with these tutorials.

These posts are primarily focused on the use of SystemVerilog in FPGA design. However, SystemVerilog is also widely used in the verification of FPGAs. If you are interested in learning more about the verification features of the language then you may also wish to take one of these SystemVerilog courses.

How to Write a Basic Module in SystemVerilog

In the first post in this series we talk about how we structure SystemVerilog designs and how this relates to the hardware being described.

An introduction to SystemVerilog Data Types

In this post we talk about the different data types which we can use in SystemVerilog based designs and testbenches.

An Introduction to SystemVerilog Arrays

In this post we talk about static arrays and how we can use them in our SystemVerilog designs

SystemVerilog Dynamic Arrays and Queues

In this post we talk about how we use dynamic arrays, queues and associative arrays in SystemVerilog

Creating Custom Types in SystemVerilog using Typedef, Enum and Struct

In this post we look at how we can create our own custom data types in SystemVerilog using enum, typedef and struct

An introduction to SystemVerilog Operators

In this post we look at the different operators which we can use in our SystemVerilog designs.

Continuous Assignment and Combinational Logic in SystemVerilog

In this post we talk about continuous assignment before looking at some of techniques we can use to model combinational logic in systemverilog

Using the Always Block to Model Sequential Logic in SystemVerilog

In this post we discuss the coding methods we can use to model basic sequential logic circuits using the SystemVerilog always block

If Statements and Case Statements in SystemVerilog

In this post we talk about two of the most commonly used constructs in SystemVerilog - the if statement and the case statement. We have seen in a previous post

An Introduction to Loops in SystemVerilog

In this post we look at the different types of loop which we can use in SystemVerilog.

An Introduction to Functions in SystemVerilog

In this post we discuss functions and how we use them to write SystemVerilog code which is reusable.

An Introduction to Tasks in SystemVerilog

In this post we look at tasks in SystemVerilog and how we use them to write code which can be reused.

Using Generate and Parameters to Write Reusable SystemVerilog Designs

In this post we look at how we use parameters and generate blocks to write reusable SystemVerilog modules.