SystemVerilog

On this page you will find a series of tutorials introducing SystemVerilog for FPGA design and verification. These tutorials take you through all the steps required to start using SystemVerilog and are aimed at total beginners.

If you haven’t already done so, it is recommended that you read the posts which introduce the FPGA development process first. These give an overview of all the stages required to design an FPGA. This information will give you some important basic background knowledge which will help with these tutorials.

These posts are primarily focused on the use of SystemVerilog in FPGA design. However, SystemVerilog is also widely used in the verification of FPGAs. If you are interested in learning more about the verification features of the language then you may also wish to take one of these SystemVerilog courses.

A picture of the underside of a CPU
In the first post in this series we talk about how we structure SystemVerilog designs and how this relates to the hardware being described.
A picture showing a pile of types faces as used in an old fashion printing press
In this post we talk about the different data types which we can use in SystemVerilog based designs and testbenches.
A metal plate with a grid of raised squares on it
In this post we talk about static arrays and how we can use them in our SystemVerilog designs
Different colored chalk stacked in a pile.
In this post we talk about how we use dynamic arrays, queues and associative arrays in SystemVerilog
A picture of a number of different hand tools hanging on the wall.
In this post we look at how we can create our own custom data types in SystemVerilog using enum, typedef and struct
A black board with 1 + 1 = 2 written on it in white chalk
In this post we look at the different operators which we can use in our SystemVerilog designs.
A picture of a number of electronic chips mounted on a PCB.
In this post we talk about continuous assignment before looking at some of techniques we can use to model combinational logic in systemverilog
The top half of an analog pocket watch.
In this post we discuss the coding methods we can use to model basic sequential logic circuits using the SystemVerilog always block
A computer screen showing the source code for an if statement
In this post we talk about two of the most commonly used constructs in SystemVerilog - the if statement and the case statement. We have seen in a previous post
Looking up at the sky from the centre of a spiralling building
In this post we look at the different types of loop which we can use in SystemVerilog.
A computer screen showing the source code for a function
In this post we discuss functions and how we use them to write SystemVerilog code which is reusable.
A notepad with the words to do written on it and a pen laying on top of it
In this post we look at tasks in SystemVerilog and how we use them to write code which can be reused.
A bag for recyclable rubbish surrounded by brown leaves.
In this post we look at how we use parameters and generate blocks to write reusable SystemVerilog modules.

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