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Learn how to use all of the different types of loop in SystemVerilog – the for loop, foreach loop, while loop, repeat loop and forever loop
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Learn how to create custom data types in SystemVerilog based designs and test benches using the typedef, enum and struct keywords
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Learn how to use tasks in SystemVerilog in order to write more efficient code which can be reused across multiple designs and testbenches.
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Learn how to write SystemVerilog which can be reused across multiple designs by using parameters and generate statements.
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Learn how to use two of the most common sequential statements in SystemVerilog programming – the if statement and the case statement
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Learn about the SystemVerilog operators and how they can be used together with the assign keyword to model basic combinational logic circuits
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An introduction to the FPGA development process featuring a detailed discussion of the synthesis, place and route, timing and verification
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Learn about the FPGA build process, including a description of the synthesis, timing analysis and place and route processes
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Learn about fixed sized arrays in SystemVerilog, including array literals, loops and the difference between packed and unpacked arrays
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Learn how to write SystemVerilog functions in order to write code which can be reused across multiple designs.