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An introduction to the FPGA development process featuring a detailed discussion of the synthesis, place and route, timing and verification
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Learn how to make use of dynamic arrays, queues and associative arrays in SystemVerilog based test benches for FPGA design
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Learn how to use continuous assignment statements in SystemVerilog in order to model the behavior of basic combinational logic circuits
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Learn about the basic data types which can be in SystemVerilog design, including the new 2 state data types such as int, logic, bit and byte
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Learn how SystemVerilog modules are used to structure designs and how this relates to the underlying hardware which is being described.
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Learn how to write efficient verilog by creating reusable code using parameters and if generate, for generate and case generate statements.
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Learn how to use the the task and function subprograms in verilog in order to write code which can be reused across multiple designs.
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Learn how to use all of the different types of loop in verilog – the for loop, while loop, repeat loop and the forever loop
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Learn how to use two of the most common sequential statements in verilog programming – the if statement and the case statement
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Learn how to write a basic testbench in verilog using initial blocks, forever loops, system tasks and delay models.