Learn how to write efficient verilog by creating reusable code using parameters and if generate, for generate and case generate statements.

Learn how to use the the task and function subprograms in verilog in order to write code which can be reused across multiple designs.

Learn how to use all of the different types of loop in verilog – the for loop, while loop, repeat loop and the forever loop

Learn how to use two of the most common sequential statements in verilog programming – the if statement and the case statement

Learn how to write a basic testbench in verilog using initial blocks, forever loops, system tasks and delay models.

Learn about the always block in verilog and how it can be used to describe the behaviour of both sequential and combinational logic circuits

Learn about the Verilog operators and how they can be used together with the assign keyword to model basic combinational logic circuits

Learn about the basic types of data, vectors and arrays which can be used in verilog including how to declare them and assign data to them.

Learn how modules are used in verilog to structure designs and how this relates to the underlying hardware which is being described.