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Learn about the always block in verilog and how it can be used to describe the behaviour of both sequential and combinational logic circuits
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Learn about the Verilog operators and how they can be used together with the assign keyword to model basic combinational logic circuits
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Learn about the basic types of data, vectors and arrays which can be used in verilog including how to declare them and assign data to them.
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Learn how modules are used in verilog to structure designs and how this relates to the underlying hardware which is being described.
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Become a more efficient VHDL designer by learning how to write reusable components using generics, the if generate statement and the for generate statement
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Learn how to use the function and procedure subprograms in VHDL and see how packaages are used to organise common subprograms
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Learn how to use some of the most common sequential statements in VHDL, including the if statement, case statement, for loop and while loop
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Learn how to write a basic testbench in VHDL using wait on, wait for, wait until and after statements to generate basic input stimulus
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Learn how to use the VHDL process keyword to execute statements sequentially and model basic sequential logic circuits such as counters.
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Learn how to use basic VHDL operators and signal assignment statements, such as when else and with select statements, to model combinatorial logic.