On this page you will find a series of Verilog tutorials that introduce FPGA design and simulation with Verilog. These Verilog tutorials take you through all the steps required to start using Verilog and are aimed at total beginners.

Verilog Video Tutorials

For a deeper dive, our exclusive Verilog video tutorials offer a deeper dive into the subjects covered in our free Verilog tutorials. The video tutorials include live coding sessions with source code that will be shared with anyone that purchases a video.

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Video Tutorials

How to Write Basic Verilog Modules

Find the source code from this video tutorial on EDA Playground

An Introduction to Data Types in Verilog

Using Continuous Assignment to Model Combinational Logic

Find the source code from this video tutorial on EDA Playground

An Introduction to Always Blocks in Verilog

Verilog Tutorials

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How to Write a Basic Verilog Module

In the first post in this series we talk about how Verilog designs are structured and how this relates to the hardware being described …

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An Introduction to Verilog Data Types and Arrays

In this post we talk about the different types we can use in verilog …

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An Introduction to the Verilog Operators

In this post we look at the different operators which we can use in our verilog designs …

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Using Continuous Assignment to Model Combinational Logic in Verilog

In this post we talk about continuous assignment before looking at some of techniques we can use to model combinational logic in verilog …

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Using the Always Block to Model Sequential Logic in Verilog

In this post we discuss the coding methods we can use to model basic sequential logic circuits using Verilog …

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How to Write a Basic Verilog Testbench

In this post we talk about testing our verilog based designs using basic test benches …

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If Statements and Case Statements in Verilog

In this post we talk about two of the most commonly used sequential statements in verilog – the if statement and case statement …

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An Introduction to Loops in Verilog

In this post we look at the different types of loop which we can use in our verilog designs …

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Using Tasks and Functions in Verilog

In this post we discuss subprograms and how we use them to write more efficient verilog code …

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Writing Reusable Verilog Code using Generate and Parameters

In this post we look at how we use parameters and generate blocks to write reusable verilog modules …

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