An Introduction to SystemVerilog Arrays
In this post we talk about static arrays and how we can use them in our SystemVerilog designs
An introduction to SystemVerilog Data Types
In this post we talk about the different data types which we can use in SystemVerilog based designs and testbenches.
How to Write a Basic Module in SystemVerilog
In the first post in this series we talk about how we structure SystemVerilog designs and how this relates to the hardware being described.
Writing Reusable Verilog Code using Generate and Parameters
In this post we look at how we use parameters and generate blocks to write reusable verilog modules.
Using Tasks and Functions in Verilog
In this post we discuss subprograms and how we use them to write more efficient verilog code.
An Introduction to Loops in Verilog
In this post we look at the different types of loop which we can use in our verilog designs.
If Statements and Case Statements in Verilog
In this post we talk about two of the most commonly used sequential statements in verilog – the if statement and case statement
How to Write a Basic Verilog Testbench
In this post we talk about testing our verilog based designs using basic test benches.
Using the Always Block to Model Sequential Logic in Verilog
In this post we discuss the coding methods we can use to model basic sequential logic circuits using Verilog.
Using Continuous Assignment to Model Combinational Logic in Verilog
In this post we talk about continuous assignment before looking at some of techniques we can use to model combinational logic in verilog
