An Introduction to SystemVerilog Arrays
In this post we talk about static arrays and how we can use them in our SystemVerilog designs
An introduction to SystemVerilog Data Types
In this post we talk about the different data types which we can use in SystemVerilog based designs and testbenches.
How to Write a Basic Module in SystemVerilog
In the first post in this series we talk about how we structure SystemVerilog designs and how this relates to the hardware being described.